CAM cell in memory and its application 2021

A content-addressable memory CAM (similar to SRAM) is an associative storage memory that addresses(searches) the content present in the computer. It compares the provided input data with the table of values and returns the address of matched data location.

Table of Contents

Basics of Content Addressable Memory(CAM)

Content-addressed memory or CAM is like the combination of an SRAM with some added searching functionality to it. It does work like an SRAM such as it can read data from the particular memory location and it can write data on the intended memory location.

Its main operation other than acting like an SRAM is performing a matching or searching operation. A valid search asserts the output match-line in other words an input value being found in the particular memory location. It compares the input data value with the lookup table.

This CAM has the ability to look for the whole table of contents in a single clock cycle.

CAM Cell Architecture( 10T CAM cell and 9T CAM cell)

10T CAM cell

1. The above structures form a CAM cell (Content Addressable Memory) which is comprised of an SRAM cell and some additional transistors which help to perform the required match operation.

2. Here more than one CAM cell in the single word line is connected or tied to the same match line, which may be pulled to High through a pseudo-NMOS gate or can be precharged.

3. If you observe the above figure the data to be searched that is key will be placed on the bit line. If this key is different from the data value stored in the SRAM cell then the match line goes to Low or will be pulled down.

4. And the match line will be pulled up or high only when all the bits of the key are matched with the data value stored in the cell array.

5. The data to be searched that is key can have don’t care value. This can be achieved by setting both bit and bit_b low.

>> The area of CAM cells will be twice the area of the SRAM cells.

9T CAM Cell

The above structure i.e. 9T CAM cell is slightly different in size as well as design from the 10T CAM cell.

key	cell data	match line
0	0	0
0	1	1
1	0	1
1	1	0

Here the logic function XOR for inputs key and cell data is performed by transistor N1 and transistor N2. As per the XOR truth table if both key and cell data are matched the output match line will be pulled down.

And if key and cell data are not matched, the transistor N3 will be turned ON and the match line output will be a degraded logic High value.

4×4 CAM cell array

A typical 4×4 CAM cell array as shown in the above figure can be comprised of either 10T CAM cells or 9T CAM cells depending on the design requirements.

It forms a typical CAM cell memory that does an associative search to find data inside it.

TLB’s (Translation Lookaside Buffer)

TLB’s are one of the applications of CAM cell memory. The above figure shows a TLB that makes use of CAM cell memory, SRAM cell array, and NOR gate to find a miss. In the microprocessor, TLB’s helps to support the virtual memory.

Let us understand the working of TLB’s here.

1. A CAM cell array in the TLB accepts the virtual memory address provided by the microprocessor as the key to be searched. If this virtual address is found in the cell array then the output match line will be asserted.

2. This match line further helps as the word line to SRAM cell array. And The associated physical address from the memory can be accessed through word line.

3. A miss signal for the CAM cell memory is generated by a NOR gate (input bubbled AND gate) as shown in the figure by processing all the match line outputs.

Cache memory in detail and hit ratio June 2021