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SOC Design Life Cycle VLSI Chip 2021

SOC Design Life Cycle VLSI Chip 2021

Basics of System on chip (SOC) design (IP based or Platform based) with the need of SOC, SOC architecture, Advantages of SOC, and various examples of SoCs available in the market are discussed here.

A System on Chip (SOC) is nothing but an integrated circuit (IC) with a full-proof system or a complete computer on a single platform chip. The SOC design may be followed as an IP-based design or a platform-based design.

SOC definition and its Need

System on chip (SOC), is an integrated circuit where all the functional elements such as dedicated hardware, processor, memory, I/O, and peripherals are embedded onto a single platform chip to meet the product design requirements.

SOC definition and its Need

Need for SOC design

1. With the advancement in the technology, it becomes the primary goal of any VLSI design engineer to have a VLSI chip that consumes very low power, matches the speed requirements with lower cost rates, and reduce the space occupied as much as possible as the device size is getting thinner and smaller.

2. Advancement in the RF CMOS technology, High density and low power techniques in the VLSI, and design reuse and reconfigurable approaches, all motivated me to go for the System on Chip (SOC) design.

3. As SOC allows us to integrate all of the essential components onto a single chip, it is very advantageous to have SOC in portable devices such as Smartphones, Tablets, and Laptops, etc.

SOC Architecture and Components

A typical SOC architecture includes several hardware and software components as shown in the below architecture and establishes the communication between all the components through buses and bus protocols.

A typical SOC architecture

A SOC is the combination of CPU processor + ASIC (Application-specific integrated circuits) + The software required to run the hardware. In general, SOC contains A main microcontroller or microprocessor or DSP core, Memory blocks, Timing circuits, Peripherals, Analog and Digital interfaces, Voltage regulators, external interfaces, and power management circuits as shown in the above block diagram.

Let us discuss briefly some of the main components of SOC design.

CPU Processor in SOC

The central processing unit is a processor that can act as the heart of the SOC. Nowadays multicore processors are in the market which provided great speed and user experience when multiple applications are running on the device. A typical processor performance diagram with 4 cores and 8 logic processors is shown below. It has three cache levels L1, L2, and L3 to enhance the data transfer performance between CPU and Memory.

CPU Performance example 4 core

Digital Signal Processor (DSP) in SOC design

An integrated circuit intended to perform operations required for Sensor nodes, Actuators, and other digital processing is known as a Digital Signal Processor DSP. DSP mainly includes data analytics and data processing functions.
These kinds of multipurpose and power-efficient DSPs are embedded in SOCs to meet the desired functional requirements. DSP also helps in reducing the CPU cycles.

Memory on SOC

Based on the design requirements and application the memory type and size will be decided on the SOC. Memory can be of volatile RAM and non-volatile ROM based on the application.
The MOS metal-oxide-semiconductor memories are preferable by the semiconductor industry as they can be designed on fabricated on a single chip. Typical memory manufacturers in the industry are micron, western digital and there are many.

SOC On-chip communication

To communicate between the different units such as CPU, DSP, Memory, and other peripherals on SOC, we have bus architecture and nowadays network-on-chip interconnect.

ARM holding provides several methods or protocols to have the bus communication between the SOC units. AMBA (Advanced microcontroller bus architecture), AHB (Advanced high-performance bus), APB (Advanced peripheral bus) and many are the bus protocol structures by ARM for bus communication. One can visit the ARM holdings website to read in detail about these protocols.

IP based SOC design

Visit this link IP design in VLSI to study in detail IP-based design and the advantages of using IP cores in the design to increase reusability and reduce time-to-market.

SOC design flow in detail

The below figure shows different stages involved in the SOC design life cycle, mostly similar to typical VLSI design life cycle or ASIC design flow.

SOC design life cycle

IP cores for the design reusability from the IP vendors can be availed in different levels of the design life cycle.

1. Soft IP core at the stage of RTL design which will be fully customizable according to the design requirements.

2. Firm IP core at the Synthesize and DFT stage can be assumed to be designed and synthesized in an accurate and optimized way by meeting standards. These firm IP cores can be customized to meet the layout design rules.

3. The hard IP core is the easiest and fixed design that can be directly placed on the layout and do the interconnections.

Let us discuss various stages of the SOC design life cycle with the input and output files and file formats at each stage.

SOC design requirements or specifications

Analysis of design requirements completely to design a product with SOC. The number of SOC components which can be reused over the design will be decided to produce as standard IPs to reduce the design time.

Usually, IPs will be provided by IP vendors or can be in-house. IP vendors can provide IP design at various stages of design such as Soft IP cores, Firm IP cores, and Hard IP cores.

RTL design for SOC

Based on the analysis of the design requirements, some parts of the design will be based on IP cores and some parts of the design would be application-specific. The IP core RTL and the RTL of the remaining design will be integrated to form a complete RTL description.

RTL description can be in any of the hardware description languages such as Verilog and VHDL and this RTL description will be verified by using various simulation tools. It is a must to write a synthesizable (which can be converted easily into equivalent digital circuits) RTL for the design.

RTL code will be in .v Verilog format.

Synthesis and SOC design integrator

Synthesis is the process in which the RTL code .v format will be converted into an equivalent gate-level circuit netlist. Synthesis involves the stages like mapping, optimization, and decomposition. SOC design integrator helps to combine the IPs and to generate the gate-level netlist.

Gate level netlist will also be in the .v format only but it mainly contains the information about the standard logic cells and digital circuit with interconnection information. Standard logic cell and I/O information will be fetched from the cell library as shown in the above figure.
DFT helps the design for testing the functionality. Refer to the article Basics of DFT in VLSI to learn in detail about design for testability.

A firm IP core is nothing but a readily available and completely tested IP till this stage of the design life cycle.

SOC design layout and STA

We can consider till synthesis the design as a front-end design and once the gate-level netlist is available we can proceed with a Physical design that is nothing but back-end design.

Physical design is a process of converting the available gate-level netlist into the physical layout for a chip following all the layout design rules. Typically physical design involves floor planning, power planning, cell placement, routing, and DRC/LVS to provide the final GDS2 layout.

You can refer to the Complete ASIC design flow for a brief understanding of physical design stages.

Static timing analysis STA is one of the very important processes in the design lifecycle. A timing check is done after every stage in the physical design to meet timing requirements. Clock tree synthesis CTS plays a very important role in timing the design correctly. You can read more on STA at STA Setup time and Hold time.

Fully tested hard IP cores will be provided by the IP vendors which meet the standard rules set by the semiconductor industries.

Fabrication of SOC

Once the GDS2 (Graphic data system formant) layout file is generated, it will be sent to the foundry. This gds2 to layout file will be standard across the fabrication industry which helps the data exchange of an integrated circuit or SOC.

SOC from the foundry will be received after several months which can be assembled and tested for the functionalities before the mass production of SOCs.

SOC Examples

Let us list out some of the available SOC’s in the market from various semiconductor companies.
A SOC from Qualcomm is Qualcomm Snapdragon S4. Qualcomm SOCs are popular in Android smartphones.
A SOC from Samsung that is Samsung Quad 4 Exynos is based on the ARM holding architecture which will enable devices capable of playing 3D games and an Extensive level of multitasking.
An NVIDIA Tegra family SOC named NVIDIA Tegra 3 is popularly used in android phones.
SOC from intel that is Intel Medfield based on x86 architecture by intel itself unlike based on ARM.
A Motorola Atrix 2 smartphone with android OS makes use of a Texas Instruments OMAP 4 SOC from TI.

Advantages of SOC over ICS

  1. SOC plays a very important role in reducing the size of an overall product. As several external components are embedded into a single IC in SOC design, the size reduces to a size of a coin.
  2. SOC uses low power design techniques to optimize the overall power consumed by a design. An example where SOCs used in cell phones helps in giving long battery life to a phone.
  3. SOC helps the design to use lesser external components and IP design techniques help to improve the design reusability this leads to a cost reduction of the overall product design.
  4. SOCs provide flexible (reprogrammable) and reliable (reduced design complexity) product designs.

Disadvantages of SOC design

  1. Compared to a specific IC design SOC design takes more time.
  2. Since several components are getting embedded into a single chip, the design fabrication cost exponentially increases.
  3. For a small number of productions, SOCs are meant to be not a good option.
  4. Design verification for the SOC is complex than for an IC.

SOC design applications

  1. SOC designs are widely used in Smartphone Industry.
  2. Nowadays smartwatches coming into the market in a wide range that makes use of SOCs.
  3. LTE and 5G communication applications make use of SOC designs.
  4. SOC designs play a vast role in embedded systems by providing smaller and single-board computers.

SOC design challenges

SOC faces various design challenges in terms of Architecture, DFT, Validation, Front end, and Back end design, System Integration, and On-chip isolation.

1. In terms of architecture, an Architecture engineer has to select what kind of processor and bus or network-on-chip communication.

2. Challenge in DFT is to various types of Faults need to be modeled and scan design techniques to be planned.

3. The validation has to be planned for the IPs used as well as the design once the IPs are integrated.

4. On-chip isolation should consider various design effects such as coupling effect, guard rings, and grounding effects, etc.

A good hardcore IP must be selected based on the following parameters in design a SOC.

  1. Configurability An IP must meet the requirements of many different designs.
  2. Standard Interface The IP cores must have the capability to integrate easily.
  3. Compliance to Defensive Design Practices IP should facilitate complete timing closure and verified and validated functional requirements.
  4. Complete Set of Deliverables must be provided by the IP vendor such as Correct code and test benches, Synthesizable RTL, Synthesis scripts, library databases, tool information, and proper documentation of all.

SOC Verification is a complex and very important part of the overall SOC design cycle. It consumes more than 70 % of the total product life cycle time in verification and validation. Verification is done at all stages of the design. Finding a fault or defect at the earliest is a good thing than finding it after the chip fabrication.

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