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Limitations of STA Timing Design

Limitations of STA Timing Design

Static timing analysis helps to find timing issues in almost all aspects of a design and is very important to have a VLSI chip with no timing problems. But there are still some cases where STA timing verification cannot be completely applied and verified. Let us discuss some of such difficulties or limitations of STA in the below article.

You can read these STA (Setup time and Hold time) and STA-related problems with solutions articles to understand static timing analysis first. Calculating maximum operating frequency and checking for setup and hold time violations are described in detail.

STA during Reset Sequence

When there is an asynchronous or synchronous reset, we need to check whether all the flip-flops got reset. The flops must reset into their required logic values. We cannot check this functionality with the STA (static timing analysis).

There is a chance that the VLSI chip may not turn up after reset. The main reason behind this is a declaration of initial values for the signals will be verified only during simulation. These initial values are not verified during design synthesis.

X – handling in STA

There are no methods to handle unknown (don’t care) values in static timing analysis (STA). STA can perfectly handle either fully logic one (logic high or rise) or logic zero (logic low or fall).

It is not possible to check in STA if an unknown value X leads to indeterminate values propagated through the design. The noise analysis part in the STA can propagate and analyze glitches in the design.

STA check when asynchronous clock domain crossing

When there is an asynchronous clock domain crossing the static timing analysis is incapable of checking whether there are proper synchronizers are in place.

With the help of other physical design or timing design tools we have to check for proper synchronizers are there in place of asynchronous clock domain crossing in all instances.

Input-Output I/O interface timing

In the STA static timing analysis constraints, it may not be possible to provide I/O interface requirements. An example where simulation of DDR (Double data rate) interface is to be done.

An SDRAM (Static Dynamic Random Access Memory) modeling can be used for this DDR simulation. This kind of simulation helps to verify whether the data is read or written onto the memory.

The timing between analog and digital interfaces

The static timing analysis STA cannot deal with the Analog interfaces or blocks. The situation when there are analog and digital interfaces needs to be verified with the help of other techniques or design methodology.

STA when there are false paths

Proper information on the false paths and multicycle paths must be provided as constraints to perform static timing analysis. A false path is nothing but when a particular logic never activates in all possible cases.

Such a path is ignored from the STA if the proper timing constraints are not given. The STA flags violation if any of the timing constraints do not meet.

FIFO pointers when out of synchronization

There is no way two determine the missing synchronization between two different finite state machines in static timing analysis. It is very important to be the finite state machines in sync during the functionality of the design that is they should be in lock-up.

It is most likely to go two FSMs out of sync when there is unwanted delay insertion. But the STA method cannot detect this kind of FSM out of syncs.

Timing in synchronous clock logic

In the sequential design circuit which has clock networks it is required to have the clock generation logic and definition of the clock must match.

The limitations of STA are that it cannot verify this match between clock definition and clock synchronization logic and static timing analysis assumes that the generated clock is correct as per the clock definition.

This will lead to timing issues when there is an insertion of logic which may increase or vary the clock’s duty cycle.

Across clock cycles

When there is a change in the functionality of the logic circuit across the clock cycles, the static timing analysis STA cannot determine this functional behavior.

Summary on STA

Even after having these set of limitations of STA (static timing analysis), STA is most popular and widely preferred by back-end timing design engineers.

Simulation with the timing or with the unit delay concept can be done to verify as a backup to STA or to manage with the above limitations. Also, normal functionality will be verified using simulation.

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