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IP Design in VLSI Process Standard 2021

IP Design in VLSI Process Standard 2021

In the modern semiconductor industry IP (Intellectual Property) based VLSI design is trending. This in the Semiconductor industry has become so important to enhance the production of VLSI chips. These designs are largely reusable in terms of logic function and design layout. It with Verification capability is termed as VIPs.

In this article, we will try to understand the design life cycle in VLSI chip design. A semiconductor intellectual property (IP) core is most widely used by the VLSI Chip Design engineers in their own product designs,

It has various aspects, In VLSI the IP is produced or being used based on the role of the design engineer. Let us understand why we need IP in VLSI, its brief history, what are the different IP cores, What can be the different IP’s in a design, the life cycle, and its usage across the semiconductor industry.

You will understand the difference between the hard IP and soft IP cores and  its life cycle in detail.

Introduction to IP design in VLSI

If we go to the early 1970s, the standard cells were being considered as reusable blocks as IP in VLSI. You can say the first IP design started with standard cells. Fixed height row cells and standard placement and routing algorithms were followed for these standard cells. The main purpose was to automated the design process of ASICs by these standard cells.

That led to increasing in the design costs compared to the manufacturing costs. A technique that trades between design and manufacturing was need by having optimized low-cost re-usable standard cell designs were expected.

In today’s semiconductor industry, we have IPs ranging from standard cells to I/O cells and processors(CPUs). The requirement for the VLSI chip engineers is increasing enormously which includes the complex level of integrations. We started expecting the VLSI IC chips to be working as systems such as System on Chips (SOCs).

Need for an IP design in VLSI

1. Designing a SOC (system on chip) mainly involves the ability of a VLSI architect who can identify a good combination of various components to place on the chip.

2. It is very important to consider these components which are open standard and must be an IP provider licensed who are great in the market(such as they provide standard instruction sets).

3. It is difficult to identify and design and IP  for product manufacture. He may not have the ability to design low-level standard IPs or he has to focus more on the product outcome by using existing standard reusable IPs. In case he can design an IP but can face legal problems and also patent violations.

4. Usually the current generation VLSI chip from the current generation becomes the IP core for the next generation as the technology is getting advanced very fast. Hence In VLSI, an IP core design is crucial in the VLSI semiconductor world to advance and meet the pace.

5. Current VLSI semiconductor world expects chip designers to have one or more CPUs and the cache in it to get the purpose fulfilled. It is very important to have reusable IPs in the design instead of starting from scratch every time to reduce the time to market the product.

6. Multicore processors (for example octa-core CPUs from Qualcomm) came into the market and they are dominating the IC and microprocessor world. The situation makes sense if the processors are replicated on the die itself.

In today’s world IP is dominating in the VLSI IC design because we are producing very advanced multicore processors. Right now we have the ability to produce several billions of transistors on a single chip. The chip design process is so advanced and automated by making use of various VLSI design tools so, it does not make any sense to search from scratch without using IP designs.

Role of IP design providers in semiconductor devices

We know that the need for IP designs in today’s VLSI semiconductor integrated chip designs, integrated devices relying on IPs as re-usable building blocks in the overall product design.
It is very time-consuming and not standard to create an IP in-house, which also allows us to forget thinking about main design requirements and overall system perspectives.

1. IP provider companies provide custom IP services and  IP verification services which make the task easier.

2. They take care of whether or not our required IP makes use of standard well-defined re-usable such as SPI interfaces or ASIC macros or Custom ADCs etc.

3. In VLSI IP providers will have design engineers who are well expertise and have complete domain knowledge who can help to achieve the desired requirements to reach a complete product.

4. IP service will also capable of providing the resources and silicon expertise needed to create an IP by using various EDA tools to analyze, simulate and verify the IP designs.

IP designs in various fields

In VLSI IP can be created in various fields of semiconductor industries to speed the design process.

A few of the IP block examples which are being spread into different fields are

  1. IP blocks in High-resolution temperature sensors
  2. Biomedical sensors are making use of IP blocks.
  3. In the analog field such as SAR-ADCs Successive Approximation, Analog to Digital Converters used IP blocks. Several designs such as Pipeline ADC’s, and Digital to Analog Converters (DAC) will include IP.
  4. Voltage circuits such as Voltage references and Voltage regulators use IP.
  5. Real-time clock circuits, Radio Frequency Identification (RFID) circuits, and IoT components make use of IPs.
  6. Core VLSI Industries use IPs for reusing in Custom Standard cell libraries, Current Mode Logic (CML) for high-speed applications, and various CMOS, LVDS, ECL I/O cells.

IP design deliverables from IP providers or IP core vendors

To use the IP design in the system-level design effectively the IP providing companies provide all the detailed components such as

  1. IP core data sheet in detail
  2. Simulated SPICE netlist of the IP
  3. IP behavioral models
  4. Timing models such as .lib, .lef of the IP will be delivered
  5. Final IP design GDS2 format to integration.
  6. Also, provide CDL(circuit design language) for LVS verification.

All the deliverables will be completely tested and characterized by the IP providers.

Types of IP design in VLSI

It is very important to design a SOC (system on chip) in a short or expected reasonable amount of time. It is not useful if the time to market is crossed as the competition is very high in the industry.

Also one cannot design all the components of SOC by hand otherwise cannot finish the task on time to manufacture. In the VLSI it is always preferred to use IP designs to enhance productivity as well as to reduce the time to market.

An IP design is pre-designed and well tested so that it can be reused in many systems efficiently. IPs can be designed in two different types.

  1. Hard IP core
  2. Soft IP core

Hard IP design

A hard IP is nothing but a pre-designed layout. The parameters such as IP block’s size, IP power consumption, and the Performance of the IP can be measured accurately as the full pre-designed layout is available from the beginning itself.

A gate-level IP component, standard cell is the best example of a hard IP.

Hard IP cores are fixed and designed by considering a specific manufacturing process, if the process has to be changed then the IP design also be further redesigned. Hence a Hard IP cores needs to comply with all the electrical and physical process standards of specific process technology.

If for example, an electrical standard says IP must be able to drive the specific load at the specific delay, then the Hard IP cores should be well defined for the standard.

An important fact is that A vendor sells a qualified (which ensures the functionality and performance goal of an IP) hard IP for a specific process and it will be licensed. The qualification rules will be set universally for a particular process which includes,

  1. Fabrication of the hard IP in the specific process technology, and
  2. The testing of the main resulting VLSI chip.

Soft IP design

A soft IP is a synthesized module with one of the HDLs (Hardware Description Languages) which can be Verilog of VHDL or some advanced HDL. The advantage of a soft IP core over hard IP is that soft IP can be targeted to new process technologies. And cons of soft IP over hard IP is that soft IP can not be as fast as hard IP and also as small as hard IP.

Most widely and numerous numbers of CPUs and logic blocks are delivered in the form of soft IPs only. Proper logic function synthesis and usage of EDA tools to place and route the design will help to implement a soft IP core.

The cost and design time of soft IP is always greater than the hard IP.

These are simple synthesizable IP blocks that will be added by tags by vendors to trace them, as they can be stolen easily by anyone.

IP design life cycle in VLSI

IP design life cycle in VLSI

The main difference between the IP design and the regular custom VLSI chip design is that intellectual property is designed before it is getting used. It takes years through several generations of technologies to design an IP after when the first IP module or specifications are defined.

The above figure shows the IP design life cycle in the VLSI industry, which is mainly divided into two parts.

  1. IP Creation
  2. IP use

IP (Intellectual Property) Creation

The IP creation stage comprises Requirement specifications for IP module creation. IP module involves all the regular design processes such as writing a hardware description language (Verilog or VHDL) by considering the specifications. The testing is given much more important at every stage in IP design process as IPs will be used extensively many times.

IP requirement specifications

To start the creation of an IP (intellectual property) design in VLSI, a proper set of requirement specifications must be given. Usually, the specification sheet will be prepared by the semiconductor integrated design owner who wants to use a specific IP with the IP vendor or provider.

The specification sheet typically should include the following points,

  1. The decision should be made that whether the design would be hard IP or soft IP.
  2. The logic functionality of the IP which we want to reuse over the overall design.
  3. The full-proof performance goals of an IP must be pre-decided.
  4. The overall power consumption of the IP.
  5. The process technology for which IP standard meets.

IP design methodology (HDL)

After deciding on module design, we need to select the design methodologies from which we can meet the desired specifications. In general, writing the HDL of IP module and testing(characterization and validation) it extensively to verify the required functionality includes here.

Documentation of the IP design

These IPs are meant to be used by others, so detailed documentation at every stage of the life cycle is very important. The vendor who provides the IP will standardize the formatting of documents and their nature over the whole organization.

IP databases

Various EDA tools require many data formats to be fed as input to them to function correctly. Hence the need for a database over the IP design life cycle is crucial.
The proper information and the description of the module will be entered into the databases. Later this database becomes the deliverable from the vendor.

IP Characterization

The operational characteristics of an IP module such as temperature variations, process parameters in the fabrication, etc.. will be determined the stage of IP characterization.
The characterization of an IP is accomplished by simulation the design extensively during all the levels such as circuit level.

IP Qualification

Any IP designed from an IP vendor should be able to work in the specified process technology. The qualification follows the characterization in the IP design life cycle.

In the Qualification, the IP module is physically tested after the fabrication process.

IP (Intellectual Property) Use

IP design resources

A large number of IP vendors are there in the current semiconductor industry such as Synopsys, Moschip, Atria, Core works, IP cores, Mobiviel, and Rambus, etc.
An individual who is expertized in the industry can also sell and it typically Soft IP.
An open-source licensing for the IP design is also available for free use from the website.

Acquiring IP design

IP acquisition is rather a time-consuming process, hence this time also must be included in the overall product design time.
Generally, fabrication industries(foundry) provide IPs such as standard cells, IO blocks, etc.. and Vendors provide soft IP but their rules, privacy policy, and terms and conditions must be met while and after acquiring the IP .

IP design examples in the VLSI industry

Standard cells as IP design

Standard cells are the first-ever designed IPs, family or series of fixed height standard cells are designed together to implement a set of logic functions. The standard cells are designed with compatible layout designs.

Register transfer modules as IP design

Several logic designs which required n replications for n bit operations can be designed using IP methodology. The basic building blocks of digital logic design such as Adders, ALUs, and Some fixed data paths can be made as IP designs as these are extensively used in the product design.

Memories as IP design

in VLSI a very important and must-use IP core is memory, as they are analog has to be carefully designed. Most memories are designed as hard IPs which should be capable of a standard set of peripheral.

CPUs as IP design

An embedded CPU on the SoC to perform specific functions is one of the critical types of IP designs. The embedded processor with the main memory, cache, and I/O devices constitute the complicated part of the design.

I/O devices and Buses as IP design

SoCs can include many I/O devices, standardizing them becomes an essential part and need to be used as IP.

IPs in VLSI must be able to follow the bus standards or bus protocols and the large part of IP macros will connect to the main module and among them through buses.

An IP core must follow some of the standard bus protocols such as AMBA, AHB, and APB which are ARM holding based protocols.
Also some of the design standards such as SPI, Ethernet, USB, and UART communication protocols.

Verification Intellectual Properties (VIPs)

As IP designs are trending in the semiconductor integrated devices, there is a need to test and verify them is increasing enormously. For this need to be fulfilled IP Vendors came up with VIPs which are nothing but Verification intellectual properties.

The VIP design life cycle is very similar to the regular IP in VSLI but the purpose of the VIP is to verify the design only. These VIPs are to be inserted into the design test bench to complete the verification process.

As verification of any design at every level of abstraction is very important, completing this verification on time is also crucial. According to the study, more than 50% of the total product life cycle is spent in verification only, of course at various levels.

Large SOC designs make use of IP as well as the VIP design environment to beat the time to market and to outcome a successful product design in VLSI.

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