The circuits which accept the input that can change at arbitrary times and produces output with a nonzero probability of Metastability are Synchronizers.

The sequential logic elements are mainly characterized by the setup and hold times. If the input data changes before the setup time the output reflects a different new value after a bounded delay.

If the input data changes after the hold time the output reflects a different old value after a bounded delay. and If the input data changes between the setup and hold time constraint or aperture then the output may be unpredictable and irrelevant. That is the output may go to a metastable state.

Now let us analyze how a Latch will respond to a voltage that will change near the sampling clock edge. The Latch can enter the metastable state so designing a synchronizer circuit that reduces the probability of metastability to Zero. No circuit is designed with metastability zero we can just reduce its probability of occurrence.

Metastability

A latch circuit is bistable that is it has two states Zero and One. When a latch enters a metastable state the output will be somewhere in between Zero and One. The below figure shows a Transparent Latch, Opaque Latch, The Latch DC characteristics and A ball delicately balanced on Hilltop.

A latch mainly consists of two switches and two inverters as shown in the above figure. The latch is transparent when the switch at the input side(sample switch) is closed and the switch at the output side is open (Hold switch). Similarly, the latch is opaque when the switch at the input side(sample switch) is open and the switch at the output side is closed (Hold switch).

The two stable states in latch are A=B=0 od A=B=VDD,

1. When the latch is opaque that is A=B, the Zero and VDD are the two stable states.

2. If there is voltage level A=B=Vm which is an invalid logic level (Other than 0 or 1) introduces Metastability. It is called Meta Stable
because these voltage levels are self-consistent and they can remain there permanently. Only a noise or any other disturbance might switch this metastable state to the stable logic level.

3. The hilltop represents the metastable state and the left-hand and right-hand sides are the two stable states.

Synchronizer

As already told the synchronizer can reduce the probability of metastability.

The above figure shows a synchronizer circuit built from two flip-flops(F1 and F2).

1. The flop F1 samples the asynchronous input(time-varying input) D.

2. The output of the flop F1 that is X may go metastable for some time, but it will go to a stable state if we wait longer.

3. The flop F2 takes the input X and produces the output Q that should be a valid stable level (0 or 1) and aligned with the clock edge.

Usually, a synchronizer has a Latency of one CLK cycle(Tc).

4. The synchronizer will fail if point X does not set to a stable logic level by the setup time before the second CLK edge.

Each one of the flops samples the input on the rising edge of the CLK when the master latch(example F1) becomes opaque. And the slave latch(example F2) passes the data to the next master latch and it does not significantly affect the probability of metastability.