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Basics of Memory Testing in VLSI Memory BIST

Basics of Memory Testing in VLSI Memory BIST

Memory is a very important component in the VLSI Semiconductor industry. In VLSI Circuits’ memories play a key role in storing huge data. Memory testing in VLSI using Algorithms and Patterns efficiently is important. Built-in self test, self diagnosis, redundancy analysis and self repair.

Various test algorithms which helps in testing of memories such as BIST compiler and BIST for RAM in Seconds. Memory faults and basics of checkerboard algorithm and march tests or algorithm will be discussed.

Introduction to Memory Testing

In the current situation the world is producing large amount of data which needs to stored in the memories. So memory technology is a growing technology in the semiconductor market. Understanding and improving the memory testing in VLSI is very important because they don’t have the logic circuits or any sequential elements like flops in them.

We have to have separate techniques, test strategies and methodologies for memory testing as they don’t have similar fault models and scan design techniques cannot be reused here. In short we cannot apply regular DFT techniques in the memory. Different fault models such as Stuck at fault, Stuck open fault, Transient faults, Data retention faults, Coupling faults, and Read disturb faults with their respective notations.

Basics of Memory Architecture

Basic Memory Model

An architecture of a memory model constitutes of an array of memory cells. The array of memory cells are in the two-dimensional form. A full address is fed to memory through an address bus to row decoder and a column decoder. Row decoder decodes the address and enables the rows based on the address. Similarly, the Column decodes the address from the bus to enable associated column cell arrays. The further memory cell is connected to A sense amplifier, which senses the data stored in the memory cell array amplify it, and sends the data out.

As shown in the above memory model the intended data can be written into the memory or the data to be read out from the memory. The Read or Write enable signal is passed to the special circuitry to perform the memory operations.

We need to test the memory whether the correct data is being written or readout of the memory which is an important task.  Basic and Typical examples of memory are 1T DRAM and 6T SRAM. Sense amplifier plays a very crucial role and amplifying the data by considering the threshold for logic 1 and logic 0. The performance of the memory is analyzed based on how many clock cycles are required to write the data into the cell and clock cycles required to read the data out of the cell.

Fault Models in the memory cell array in Memory Testing

One needs to understand the various fault models used in the memory testing unlike fault models in the DFT of regular combinational circuits and sequential circuits(That is fault models, in this case, are differently analyzed as memories don’t have logic gates).
Before understanding the fault models we need to understand the notations

1. An up arrow ↑ denotes the rising transition during a write operation.
2. A down arrow ↓ denotes the falling transition during read operation.
3. An up/down arrow denotes either rising or falling transition.
4. Reversed A ∀ denotes any operation at the cell.
5. <S/F> denotes the operation activating the fault upon the faulty value of the memory cell.

Now let us list out the fault models in the memory testing,

SAF – Stuck at fault

Here there can be two faults, a stuck at 1 fault and a stuck at 0 fault. The notation for these can be, for stuck at 0 its < ∀/0 > which says for any operation on the cell, the cell response is 0 only. And for stuck at 1 its < ∀/1 > which says for any operation on the cell, the cell response is 0 only.

SOF – Stuck open fault

A stuck open fault occurs when there is a discontinuity in a word line or a switch got permanently open.

TF – Transient Faults

Here there can be two faults, a rising transient fault, and a falling transient fault. The notation for these can be, for rising transient fault its < ↑/0 > which says for the rising operation of the cell, the cell response is 0 only which has to 1. And for falling transient fault its < ↓/1 > which says for falling operation of the cell, the cell response is 1 only which has to be 0.

DRF – Data Retention Fault

This kind of fault model arises if a cell becomes incapable to hold the data or retain the data for a specified period of time. here the memory cell loses its data spontaneously and not because of READ or WRITE operations.

CF – Coupling faults

There are three kinds of coupling faults
1. Clin – Inversion Coupling fault, This kind of fault occurs when one cell transition leads to an inversion of other cell content.
2. CFid – Idempotent Coupling fault, This kind of fault occurs when one cell transition leads to a constant value either 1 or 0 in other cell content.
3. CFst – State Coupling Faults, — Here the coupled cell is forced to a particular value only if the coupling cell is in this state; <0;0/1>, <1;0/1>, <0;1/0>, or <1;1/0>.

RDF – Read Disturb Faults

This kind of fault occurs during read operation. If the cell value is getting continuously flipped during the read operation we say it as Read disturb fault (RDF).


Test algorithms are required to do memory testing in VLSI to reduce the time complexity and to cover all the possible fault models such as SAF – Stuck at faults, CFs – Coupling faults, and AFs –  Address decoder faults.

Let us take an example summary table which shows the different sized memory being tested using different memory algorithms with their time complexities. For the below table of calculations, the patterns are applied at the rate of 100M read or write operations per second.

Memory Size      n

Time Complexity n

Time Complexity n log n

Time Complexity n^1.5

Time Complexity n^2

1 Kilo Byte

0.0001 seconds

0.001 seconds

0.0033 seconds

0.105 seconds

1 Mega Byte

0.102 seconds

2.04 seconds

1.83 minutes

1.27 days

1 Giga Byte

1.75 minutes

52.48 minutes

40.8 days

3659 years

From the above table, we can assume how long memory testing may go if a proper test algorithm is not used. Anything which is going in several days and years is not linear in time. Such algorithms are not tolerable and not accepted by the industry.

One of the simplest test algorithms which are linear in time and can detect all king of faults such as SAF – Stuck at faults, CFs – Coupling faults, and AFs –  Address decoder faults is March Tests or Marches.

Now let us understand the basics of March Tests and the notations used in Marches.

March Testing Algorithms and March Patterns in Memory Testing
March tests -> March elements -> Operation on memory cell of a memory cell array.

1. A March test constitutes of a sequence of a finite number of March Elements
2. A March Element constitutes a sequence of a finite number of Operations.
3. Each Operation constitutes a number of reads and write operations.

March Test Notations

March operation may consist following set of tasks,
1. Writing a logic 0 into a memory cell – w0
2. Writing a logic 1 into a memory cell – w1
3. Reading a required 0 from the memory cell – r0
4. Reading a required 1 from the memory cell – r1
5. March element is done in the ascending order of the address –
6. March element is done in the descending order of the address –
7. March element is done in either order of the address – An Bidirectional Arrow

MSCAN – Memory Scan Algorithm in Memory Testing

Let us understand one of the memory RAM test algorithms or patterns that is MSCAN also known as a zero-one algorithm. A zero-one algorithm is nothing but a sequence of March operations or a March element.
March notation for the zero-one algorithm can be written as below,

{(w0); (r0); (w1); (r1);}

The MSCAN –  Memory scan algorithm (pattern) follow the above March element which is the finite sequence of ascending ordered write and read operations on the memory cell.
First, write 0 into a memory cell
Second, read the 0 from the memory cell
Third, write a 1 into a memory cell
Fourth read 1 from the memory cell,
and all these are done with the address in ascending order.

Limitations of zero-one or MSCAN algorithm.

1. The time complexity of the zero-one algorithm is in the order of 4N that is O(4N). where N is the number of memory cells in the memory cell array and 4N total number of read/write operations. we can say the estimated time to complete the test would be very high.

2. Not all of the Coupling faults CFs and Transient faults TFs can be covered by using the MSCAN test algorithm. Also, not all of the Address decoder faults AFs are not covered with this test pattern algorithm.

Checkerboard Algorithm or Patterns in Memory Testing

The checkerboard algorithm is similar to the MSCAN algorithm. The checkerboard algorithm is also known as the checkerboard pattern. The main difference between the zero-one algorithm and checkerboard pattern is that the zero-one algorithm writes all 0’s and all 1’s patterns(also known as solid background) and the checkerboard algorithm writes 1’s and 0’s in the alternative memory cell array locations in the checkerboard pattern.

Benefits of checkerboard algorithm or pattern over MSCAN

1. The time complexity of the checkerboard algorithm is the same as a zero-one algorithm that is O(4N).
2. The checkerboard algorithm is mainly used for detecting faults which are resulting from leakage, shorts between cells, and data retention faults.
3. The checkerboard pattern also detects SAFs – Stuck at faults and half of the number of TFs – Transient faults.
A true physical checkerboard must be created while applying the checkerboard pattern or algorithm, not the logical one.

Checkerboard pattern

There are several algorithms or patterns such as ping-pong or galloping pattern generally known as GALPAT,  and walking pattern (WALPAT) with their time complexities O(4N^2) and O(4N^1.5) respectively.

March Test – bit-oriented March C algorithm in Memory Testing

In a March Test C algorithm, there are six march elements and all of the order/direction oriented, unlike the MSCAN algorithm.

(w0); – M0 March Element

⇑(r0w1); – M1 March Element

⇑(r1w0); – M2 March Element

⇓(r0w1); – M3 March Element

⇓(r1w0); – M4 March Element

(r0); – M5 march Element

I hope by now you were able to understand the notations, you are able to clarify the purpose of each of the above march elements.
The time complexity of the March Test algorithm is 10N, where N is the number of memory cells in the memory cell array.

Benefits of March Test Algorithm

1. The March test completely detects all the fault models such as SAF – stuck-at faults, unlinked address decoder faults AFs, and unlinked Transient faults TFs.
2. It also detects all the CFs- coupling faults such as CFin – Inversion Coupling faults, CFid – Idempotent Coupling faults, and CFst – State Coupling Faults.
3.  To detect SOFs – Stuck open faults from the memory cell memory cells M1 and M2 are to be extended as shown below,
from ⇑(r0w1); – M1 to ⇑(r0w1r1); – M1 March Element extended and
from ⇑(r1w); – M2 to ⇑(r1w0r0); – M2 March Element extended.
4. The current March C algorithm can be modified to work with word-oriented memories, as shown below
Modified March C algorithm
Here the idea is to replace 0 with a and 1 with a’ from the existing March C Algorithm, where a is a data word.

Faults Simulator in Memory Testing – RAMSES

RAMSES is a memory fault simulator that is very fast which takes the memory specifications, the test algorithm used to detect faults, and fault descriptors as input to a RAMSES simulation engine to provide the fault coverage report. Below is the block diagram for RAMSES inputs and outputs.

RAMSES Fault Simulator in Memory Testing

Here the fault descriptor comprises of four different attributes,
1. Aggressor (AGR) – which activates the fault.
2. Victim (VTM) – which is affected by fault.
3. Suspect (SPT) – the possible location of AGR aggressor.
4. Recover (RCV) – A recovered victim VTM

Memory BIST Built-Inn Self Test) Model in Memory Testing

MBIST in Memory Testing
The above block diagram shows the model for memory BIST Built-In Self Test. A memory that is capable of self-test BIST, self-repair BISR, and self-diagnosis BISD is a complete product in the form of a storage element.
Inserting a self-testing circuitry in the module which acts asana interface between the Host and the memory chip. Testing on a fabricated chip with no self-test mechanism in the memory leads to complexity on the tester. Also increase the time-to-market and cost off the product.
Hers, BAC that is BIST activation control activates the BIST logic, the memory goes to normal mode when BAC = 0, and the memory goes to BIST mode when BAC = 1. The BIST controller is nothing but FSM – finite-state machine, Finite state machine provides the test pattern to the memory to test it and hence reduces the effort required to provide test patterns externally.
The BIST controller’s state flow and the transition is mainly controlled by the input BCS that is BIST control selection, which also take care of the scan chain, test pattern and command required for the self test. The scan chain have the scan input as BSI – BIST scan input  and scan output as BSO – BIST scan output.

Conclusion to Memory Testing

So far we have discussed single cell(bit-oriented memories) fault models in the article. These fault models also applies to word-oriented memories. Coupling faults in the bit-oriented cells which are discussed above have the same behavior between the words of the cell as in between the bits of a cell.
The faults mainly occur in the address decoder hence the name address decoder faults (AFs), there are several faults that can occur in the read-write circuitry and DRAM core of the memory cell array.

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