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Method of logical effort | Multi-stage networks

Method of logical effort | Multi-stage networks
Designing a circuit with great speed or to meet the delay constraints, we need to find the fastest logic function. The optimized implementation of a logic function with great speed is a key task. The method of logical effort is the easiest way to calculate the delay in the MOS circuit.
This method specifies the proper number of various logic stages on a path and the appropriate size of the transistor for the gates. Let us see how we can calculate the delay of the circuit and what are parameters we need to know.

1. The delay in a logic gate (d)

The delay in a logic gate is mainly due to two components. The parasitic delay (p) and the stage effort/effort delay (f).

d = f + p………………1

Here, the parasitic delay p is the fixed part and the effort delay is proportional to the load on the logic gate’s output.

2. The effort delay (f)

The effort delay f mainly depends on the load and also on the properties of the logic gate which is driving the load. Here two terms come into the picture. One the logical effort (g) which captures the properties of the logic gate and Second the electrical effort (h) or also called fanout which characterizes the load on the logic gate’s output.
The effort delay is related as the product of logical effort g and electrical effort h, that is

f = g * h………………..2

Further, the electrical effort h or fanout can be calculated as

h = Cout/Cin……………3

Where Cout is the capacitance at the output logic gate and Cin is the capacitance of the logic gate at one of its input terminals. The electrical effect is normally expressed in terms of the widths rather than the ratio of the actual capacitors. But here we are using the ratio of the actual capacitor because the capacitance of the transistor gate is proportional to its area. and most of the time length of the MOS transistors in the logic gate will be the same so, the capacitance is proportional to the width of the transistors.
Substituting equations 2 and 3 in equation 1 we will get,

d = g * h + p………………4

3. The logical effort (g)

The logical effort (g) for the inputs of the CMOS logic gate
1. Inverter: The inverter logic effort g is always 1
2. Multiplexer: The multiplexer logic effort is always 2
3. NAND gate: The generalized formula is (n+2)/3, where n is the number of input terminals. That is for example for n = 2, g is 4/3 and for n = 3, g is 5/3, etc.
4. NOR gate: The generalized formula is (2n+1)/3, where n is the number of input terminals. That is for example for n = 2, g is 5/3 and for n = 3, g is 7/3, etc.
5. XOR gate: The logical effort g is 4 for two input XOR. g is 12 for three input XOR, g is 32 for four input XOR.

4. The parasitic dealy (p)

The parasitic delay p for the various logic gates is given in terms of the parasitic delay of the inverter. A typical parasitic delay of the inverter is 1.
  1. INVERTER: Pinv
  2. n-input NAND: n * Pinv
  3. n-input NOR: n * Pinv
  4. n-way MUX: 2 * n * Pinv
  5. XOR and XNOR: 4 * Pinv
The method of logical effort for multi-stage logic networks calculates the best number sizes that must be used in the network. And it shows the way of balancing the delay among the different stages to get the least delay of the overall circuit. Here, the calculation of logical effort g differs as in the calculation of logic effort g in the single-stage logical network.
The path logical effort through a path is the multiplication of various logical efforts gi of all the logic gates along that path. Here the logical effort is denoted as the G and it is called a path logical effort instead of simply logical effort.

G  = prod(gi)…………..1

And the path electrical effort H along a path through the network is the ratio of the capacitance loading the last logic gate Cout to the capacitance at the input of the first logic gate in the same path.

H = Cout / Cin…………..2

Here Cout and Cin represent output capacitance and the input capacitance of the whole path.

1. The branching effort (b) and path branching effort (B)

To calculate the fanout within a network we need to include a new kind of effort known as branching effort (b). When the fanout occurs within the logic network, we need to analyze the drive current along the path. And if the path we are working on does not a branch or divide then the branching effort will be 1. The branching effort b can be written as

b = (Con_path + Coff_path) / (Con_path)…………..3

where Con_path is the capacitance along the analyzing path and Coff_path is the load capacitance along the off-path we are analyzing. The whole path branching effort is known as path branching effort and denoted as B. The path branching effort B is the multiplication of all the branching effort b at each of the stages along the path.

B = prod(bi)…………..4

2. The path effort (F)

As stage effort (f) in the single-stage logic network here comes, the path effort F for multi-stage logical network and is given by

F = G * B * H…………..5

where G = path logical effort, B = path branching effort, and H = path electrical effort or fanout.
The electrical effort of each stage is determined by the relation

B * H = (Cout/Cin) * prod(bi) = prod(hi)…………..6

3. Estimation of the path delay D

It is the sum of delays of each stage logic along the path. The relation for path delay D is

D = sum(di) = DF + P…………..7

where DF is the path effort delay and P is the path parasitic delay.
The DF (path effort delay) is simply given by

DF = sum(gi * hi)…………..8

and the P (path parasitic delay) is simply given by

P = sum(pr)…………..9

The delay is minimum when the stage effort f’ is

f’ = gi * hi = F^(1/N)…………..10

where N is the number of stages in a multi-stage network.
Therefore combining all the equations from 1 to 10 the principle method of logical effort for the multi-stage network is obtained which is the minimum delay achievable along a path. The expression for this can be written as

D’ = N * F^(1/N) + P…………..11

If we observe the equation 11 when N = 1 it becomes similar to the equation for single stage delay equation d = f + p.
To determine the input capacitances or the transistor sizes we can use the modified formula 12. Here we need to start from the end of the path and working backward then applying the input capacitance formula.

Cin_i = (Cin_i * gi) / f’…………..12

This input capacitance can be distributed among the connected transistors to the input.

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