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Complete ASIC Design flow 2021

Complete ASIC Design flow 2021
This is the standard VLSI design flow that every semiconductor company follows. The complete ASIC design flow is explained by considering each and every stage.
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Let us assume we all are IC design engineers, So you are getting the specification from the customer say to design a full adder.

For example, the customer says to design a Full adder with 2GHz or 5GHz frequency. So the specification is the first stage in any ASIC design. The specification may be the power or chip area or the chip speed.

Microarchitecture design

There will be a top-level design engineer in any company that decides the microarchitecture for the specification is whatever given by the customer.

He will design the sample architecture which contains for example for a full adder, there will be two half adders, and standard cell (OR gate), and CLK1, CLK2, etc.

Then he will estimate the chip area, speed, and power based on this model and discuss the approximate cost of the design with the customer.

Once the customer is happy with the microarchitecture was developed by the IC design engineer he will give a green signal to start the design. If the microarchitecture is finalized by the customer we have to go for the RTL design.

RTL Design

from the microarchitecture, each and every module is assigned to different low-level design engineers. So the work is divided into different groups.

The different groups will design the RTL register transfer level design.

Which is the first stage of Technology independent design? The RTL may be designed using any of the Hardware Description Languages such as Verilog or VHDL. Make sure that while going for ASICs design we need to write synthesizable RTL.


Once the RTL is designed we need to verify the design for its functional working that is we need to go for simulation.

Once the functionality is verified we need to go for the process called synthesis. Till now the design was Technology independent design. The output file will be available in the dot V(.V) Verilog format.


The moment the design is taken into synthesis the design is called Technology dependent design.

Synthesis is a three-stage process Translation, Optimization, and Mapping into the particular technology 32nm or 45ns or 50nm, etc. Once the synthesis is over we need to generate two different files.

Gate level Verilog netlist (.Vg)

SDC (Synopsys design constraint) constraint file, where need to specify input delay, output delay, clock period, is there any multicycle path? , is there any false path? Latency, Clock uncertainty, etc.

The software used for synthesis is the Design Compiler by Synopsys. Once the synthesis is over we need to move to DFT(Design for Testability).

Design for Testability (DFT)

In DFT we have to measure the controllability (ability in setting the input) and observability (ability in seeing the output from any internal node) of our design. How far our design is achievable in terms of the error rate.

Once DFT is finished we have to generate the file called ATPG (Automatic Test Pattern Generation) file.

The software normally used for DFT is Encounter Test that is from the cadence.

Up to this, we can call our design as FRONT END ASIC design.

Data Preparation

Before moving to Back end design we need to data preparation that is making sure all required files are available to start with the back-end design.

The software which is used for Back End Design is SOC Encounter and PnR Tools.

Data files required: .Vg, .SDC, .ATPG, .lib, .lef, .io

Library file (.lib) towards particular technology, if your working for a 45nm technology we need a 45nm technology library file. The library file will be of three kinds slow, typical, and fast library based on the different PVT.

Library exchange format (.lef) contains metal and via information, height and width of the cell, the width of the polysilicon, and all technology-related information.

Before going to the next stage we need to check the design at all different instances whether the synthesis fellow gave the correct netlist or not. Command to do the check design is check design – all. Once we confirm everything is okay, we need to proceed with Timing the design.

Timing Design

The design is divided into four different paths.

  1. Input to Register path
  2. Input to the Output path
  3. Register to Register path
  4. Register to the Output path

Then we will apply setup and hold predefined equations to check the Maximum frequency of operation or Minimum required clock period, Check for the violations, etc. it will come out with the slack.

If the slack is positive then it’s fine. If the slack is negative we need to optimize the design and make slack to be positive.

The timing will be verified in five different stages PRE-PLACE, PRE-CTC, POST-CTS, POST-ROUTE, and POST-SI.
Here at this stage, we do the PRE-PLACE timing check. Once PRE-PLACE is confirmed we need to go for the stage called floorplanning.


This stage involves identifying the right place for the components and placing the highly connected components close together to reduce the interconnect delay.

Power Planning

The main aim of the power planning is to reduce the IR drop. We have to make sure the same supply voltage VDD reaches to each and every component in the design.

Suppose if we are going for 180nm the allowed VDD is 1.8v. To reduce the IR drop introducing VDD VSS stripes is one of the methods. Based on complexity we can introduce only vertical stripes or both vertical and horizontal VDD VSS stripes.

Place Design

Once the floorplanning and power planning are over we will go for placement of the design. Place design places all our components standard cell, Hard macros, Soft macros, and everything into the chip. We have two options while placement.

Time-based, The focus is to improve the speed of the chip design.
Congestion-based, The main focus is to reduce the area of the chip.

Once the placement is done, we need to go for the PRE-CTS time design check. Verifying all the paths and confirming no violations and the slack is not negative.

Clock Tree Synthesis (CTS)

Trying to obtain the ZERO clock skew by inserting the clock buffer or inverter. Which may lead to timing violations, So, we need to do the POST- CTS timing design check.


There are two stages in routing the first one is Global Routing, identifying the optimized way of interconnections. and the second one is Detailed Routing, this is the actual routing between the components that are routing of signal lines, clock paths, and power wires (we need to make sure the width and length of the wire).

Routing may introduce timing violations so we need to do a POST-ROUTE timing design check once the routing is over.


The design is checked for the DRC (Design Rule Check) violations and LVS (Layout vs Schematic) violations.

Signal Integrity (SI)

The signal integrity fellow makes sure there are no issues such as Crosstalk, Noise, Migrations, and Antenna effects. To resolve these issues if had, there may be the addition or deletion of some components, which may lead to timing error.

So the design is verified by the POST-SI timing design check at this stage.

Now the design will be sent to fabrication for Tape out. and they will return us the GDSII version of the design.

Reference :
Youtube: ASIC Design flow by Ravi S

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