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Latchup and its prevention in CMOS

Latchup and its prevention in CMOS

Latchup is the most common problem in the CMOS transistor. Mainly causes due to the formation of BJTs (PNP and NPN) and can be prevented using Guard Rings.

First of all, this is the most important VLSI interview question. Most of the interview guys prefer to ask this question to check the basics of the candidate regarding MOS and its second-order effects.
You must also read these topics which I am listing below.

1. Non-ideal characteristics of MOSFET such as Velocity Saturation, Mobility degradation, Channel length modulation (CLM), body effect, subthreshold conduction, DIBL (Drain induced barrier lowering), BTBT (Band to band tunneling), GIDL (Gate induced barrier lowering),
2. the Tunneling effect,
3. Latchup,
4. Stack effect,
5. Charge sharing effect,
6. Short channel effects, and Narrow channel effects.

Table of Contents


Latchup is a condition in which the parasitic components such as PNP and NPN transistors give rise to the establishment of low resistance conducting path between VDD (Supply) and GND (ground).


The above circuit shows a CMOS Inverter circuit and the parasitic components. In addition to PMOS and NMOS, the circuit is composed of an NPN transistor, a PNP transistor, and two resistors connected between power and ground rails.

The NPN transistor is formed between the Grounded N diffusion source, P substrate, and N-well. and The PNP transistor is formed between P-type drain, N-well, and P substrate.

And the 2 resistors are due to resistance through the substrate of MOS, resistance through the substrate, and well taps. The cross-coupled transistors form a Bistable Silicon Controlled Rectifier (SCR) and ordinarily, both BJTs are off.

Latchup Cause:

Latchup can be triggered when the transient currents flow through the substrate during normal chip power-up.
Or When external voltage outside the normal operating range is applied.

Latchup effects:

If the substantial current flows into the substrate Vsub (Substrate voltage) will rise, turning ON the NPN transistor. this pulls current through the Rwell resistor bringing down Vwell and turning ON the PNP transistor.

The PNP transistor’s current intern rises Vsub, initiating the +ve feedback loop between VDD and GND, which persists until the power supply is turned off or the power wires melt.

Latchup prevention techniques:

1. Reducing Rsub (Substrate Resistance) by making High Substrate doping level and Reducing Rwell (Well Resistance) by making low resistance contact to (GND) that is place substrate and well taps close to each other.

2. Input-Output (I/O) pads are essentially susceptible to Latchup because external voltages can ring below GND or above VDD, which causes forward biasing the junction between Drain and Substrate or Drain and well and injecting the current into the Substrate.

3. Guard rings should be used to collect the currents.

4. SOI (Silicon on Insulator) avoids Latchup entirely because they have no parasitic bipolar structures.

5. The process with VDD less than 0.7volts is immune to Latchup because BJT never has a large Base to Emitter Vbe to turn ON.

6. The n-type transistors or NMOS transistors must be clustered together near the Ground and PMOS transistors must be clustered together near the Supply Voltage VDD.

Each and every well must have at least one tap in it. and A tap must be placed for every 5 to 10 transistors.

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