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Dynamic Power dissipation in CMOS

Dynamic Power dissipation in CMOS
The CMOS dynamic power is the power dissipated when the logic gate is in the active state. It is mainly due to the switching activity of the i/p signal or mainly due to the charging and discharging of internal node capacitances.
Pdynamic = ∝ * CL * (Vdd)^2 * f
The CMOS dynamic power (Pdynamic) dissipation is mainly due to
  1. The charging and discharging of the load capacitances as the gate switches from one logic to another logic.
  2. The short circuit current or leakage current while both PMOS and NMOS stacks are partially ON when not necessary.

Activity Factor (∝)

The clock gating techniques

It will disable the clock to the IDLE portions of the design and hence reducing the power dissipation because of the charging & discharging of the circuit which is not in use. That is the clock is sensitively stopped for the IDLE part of the circuit by using the EN (Enable) signal.
The clock n/w has an activity factor ∝ = 1 and a very high capacitance. Therefore it will save significant power.

Switching Probability

The activity factor ∝ of a node is the probability that it switches from logic 0 to logic 1. This probability mainly depends on the logic function of the design. ∝i = Pi’ * Pi Pi is the prob. that the node is logic 1 and Pi’ is the prob. that the node is logic 0.

The power estimation requires the guessing of an activity factor ∝ before the RTL(Register transfer level) code is been written.
The activity factor ∝ = 0.1 is a reasonable choice in the absence of better data.


The logic gates sometimes make unnecessary transitions called Glitches when the input does not arrive simultaneously. The chain of logic gates is particularly prone to this type of problem.
These glitches can cause the activity factor ∝ to rise to more than 1 & account for more power dissipation.
This glitching power can be accurately accessed or recognized through the timing analysis.

Load Capacitance (CL)

Both the device and the interconnect capacitances affect the parasitic load capacitance. The device capacitances Cgd, Cgb, and Cdb can be decreased by properly sizing transistors.

But doing so also affects the performance of the design because it decreases the driving current of the circuit. By calculating the slack time at each gate connected is one of the solutions. The load capacitance CL can be reduced by properly choosing optimized and fewer stages of logic and smaller transistors.

The Supply Voltage VDD

The supply voltage VDD has a quadratic effect on the dynamic power dissipation, Therefore selecting the lower power supply reduces the power consumption. That is why we are moving towards a low power circuit design.

The IC chip can be divided into multiple voltage islands or multiple voltage domains. And these can be used for different functional blocks of the design for reducing power consumption.

Frequency of operation (f)

The CMOS dynamic power dissipation is directly proportional to the frequency of operation. So a chip should not run faster than the necessary speed.

Also, an IC chip can use multiple frequency domains so that certain parts of the design can run at different speeds. The idea is to the part where we can afford to run slowly compared to others can be made to run slower by the concept of multiple frequency domains.

These low-frequency domains save power by making use of smaller transistors.

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