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Stack effect and Charge sharing problem in Dynamic CMOS

Stack effect and Charge sharing problem in Dynamic CMOS

The stack effect is often advantageous (reduces DIBL effect) and whereas Charge sharing is a problem to us (very critical in dynamic and semi-dynamic circuits).

Stacking effect in CMOS

The leakage through two series OFF transistors is much lower than that of a single transistor because of the Stack effect.

The below figure (a) shows two series OFF transistors with their Gate terminals at ZERO volts.

stack effect vlsiuniverse

The drain of N2 is at VDD, so that the stack will leak because of DIBL (Drain induced barrier lowering), However, the middle node Vx settles to a point that each transistor has the same current.

If Vx is small, N1 will see a much smaller DIBL effect and it will leak less.

As Vx rises, DIBL (Gate to source) voltage for N2 becomes negative, reducing its leakage.

Hence we would expect series transistors will leak less.

Stacks with three or more transistors will have even lower leakage compared to the lower number of transistors i.e. two.

Charge sharing problem in dynamic CMOS

A dynamic logic CMOS inverter driving a transmission gate leads to the Charge sharing problem.

charge sharing problem in dynamic cmos vlsiuniverse

Here, suppose a dynamic CMOS logic gate has been precharged and the output is floating HIGH and Capacitor Cx charges. Further, suppose the transmission gate is OFF and output Y equals Zero.

Now if the transmission gate turns ON, the charge will be shared between Cx and Cy and that will disturb the dynamic output.
CMOS dynamic latch circuits have the charge-sharing problem and the leakage current problem.

The charge-sharing problem may degrade the noise margin of the latch circuit. The leakage current problem limits the lower bound of the operating frequency.

Charge sharing can cause very serious operation problems, especially for semi-static circuits.

The dynamic logic circuits also suffer from charge leakage on the dynamic node of the circuit.

If this node is precharged to High voltage initially and then left that node floating, the voltage on this dynamic node will change due to the subthreshold, the gate (G), and the junction leakage.

The delay will further change from milliseconds to nanoseconds depending on the process and the temperature. This problem is quite similar to the leakage in dynamic RAMs (Random access memories).

The dynamic circuit also has poor input Noise Margins and if the input rises above the threshold voltage while the gate is in evaluation then the transistors at the input side will turn on weakly and which can discharge the output incorrectly.

By using the Keeper circuit both leakage and Noise margin problems can be resolved. Here the Keeper is nothing but a weak transistor that holds the output at the right level allowing it not to float.

These keepers transistors are usually on the order of one by tenth the strength of the pull-down stack network. For the small-sized dynamic logic circuits, the keeper transistor must be weaker than a minimum sized transistor. This will normally be achieved by increasing the keeper length.

Charge sharing problems, Noise problems, and Race problems mainly cause because of Dynamic CMOS logics, further, these can be reduced by modifying the circuit.

TIP: Study all the second-order effects of MOSFET perfectly. The second-order effects are very important for the interview. Most of the companies will ask Latchup problems and Charge sharing-related questions.

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